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MC14007UB Dual Complementary Pair Plus Inverter
The MC14007UB multi-purpose device consists of three N-channel and three P-channel enhancement mode devices packaged to provide access to each device. These versatile parts are useful in inverter circuits, pulse-shapers, linear amplifiers, high input impedance amplifiers, threshold detectors, transmission gating, and functional gating.
http://onsemi.com MARKING DIAGRAMS
14 PDIP-14 P SUFFIX CASE 646 MC14007UBCP AWLYYWW 1 14 SOIC-14 D SUFFIX CASE 751A 1 14007U AWLYWW
* Diode Protection on All Inputs * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Capable of Driving Two Low-power TTL Loads or One Low-power * *
Schottky TTL Load Over the Rated Temperature Range Pin-for-Pin Replacement for CD4007A or CD4007UB This device has 2 outputs without ESD Protection. Anti-static precautions must be taken.
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 260 Unit V V 14 mA mW C C C SOEIAJ-14 F SUFFIX CASE 965 1 A WL, L YY, Y WW, W TSSOP-14 DT SUFFIX CASE 948G
14 14 007U ALYW 1
MC14007U ALYW
= Assembly Location = Wafer Lot = Year = Work Week
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
ORDERING INFORMATION
Device MC14007UBCP MC14007UBD MC14007UBDR2 MC14007UBDT MC14007UBF MC14007UBFEL Package PDIP-14 SOIC-14 SOIC-14 TSSOP-14 SOEIAJ-14 SOEIAJ-14 Shipping 2000/Box 55/Rail 2500/Tape & Reel 96/Rail See Note 1. See Note 1.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
(c) Semiconductor Components Industries, LLC, 2000
1
August, 2000 - Rev. 4
Publication Order Number: MC14007UB/D
MC14007UB
PIN ASSIGNMENT
D-PB S-PB GATEB S-NB D-NB GATEA VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD D-PA OUTC S-PC GATEC S-NC D-NA
D = DRAIN S = SOURCE
SCHEMATIC
14 13 2 1 11
6
12
7
8
3
4
5
10
9
VDD = PIN 14 VSS = PIN 7
A B 12 1 C INPUT VDD 14 3 5 2 4 9
A
B
C 11 13
INPUT OUTPUT CONDITION 1 0 A = C, B = OPEN A = B, C = OPEN
INPUT
6
8
10
Substrates of P-channel devices internally connected to VDD; substrates of N-channel devices internally connected to VSS.
7
VSS
Figure 1. Typical Application: 2-Input Analog Multiplexer
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II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIII I IIII I IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIII I IIII I IIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I IIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I IIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I IIII I IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII I II I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III III I I I I I I I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIII II I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. The formulas given are for the typical characteristics only at 25_C. 6. To calculate total supply current at loads other than 50 pF:
where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.003.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Gate) (CL = 50 pF)
Quiescent Current (Per Package)
Input Capacitance (Vin = 0)
Input Current
Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
Input Voltage (VO = 4.5 Vdc) (VO = 9.0 Vdc) (VO = 13.5 Vdc)
Output Voltage Vin = VDD or 0
(VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)
(VO = 0.5 Vdc) (VO = 1.0 Vdc) (VO = 1.5 Vdc)
Vin = 0 or VDD
Characteristic
IT(CL) = IT(50 pF) + (CL - 50) Vfk
"1" Level
"1" Level
"0" Level
"0" Level
Source
Sink
Symbol
VOH
VOL
IOH
VIH
IDD
Cin
IOL
VIL
Iin
IT
VDD Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
--
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- 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95
MC14007UB
4.0 8.0 12.5
0.64 1.6 4.2
MinIII Max
-- -- --
--
--
-- -- --
-- -- --
- 55_C
3 0.1 0.25 0.5 1.0 0.05 0.05 0.05 1.0 2.0 2.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 4.0 8.0 12.5 0.51 1.3 3.4 IT = (0.7 A/kHz) f + IDD/6 IT = (1.4 A/kHz) f + IDD/6 IT = (2.2 A/kHz) f + IDD/6 Min -- -- -- -- -- -- -- -- -- -- -- 0.00001 Typ (4.) 0.0005 0.0010 0.0015 25_C - 5.0 - 1.0 - 2.5 - 10 2.75 5.50 8.25 2.25 4.50 6.75 5.0 1.0 2.5 10 5.0 10 15 0 0 0 7.5 1.0 2.0 2.5 -- -- -- -- -- -- -- -- -- -- -- -- -- 0.1 0.25 0.5 1.0 0.05 0.05 0.05 Max - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 4.0 8.0 12.5 0.36 0.9 2.4 Min -- -- -- -- -- -- -- -- -- -- -- 125_C 1.0 0.05 0.05 0.05 Max 7.5 15 30 1.0 2.0 2.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- mAdc mAdc Adc Adc Adc Unit Vdc Vdc Vdc Vdc pF
MC14007UB
IOH , DRAIN CURRENT (mAdc)
IOL , DRAIN CURRENT (mAdc)
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIII I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
Characteristic Symbol tTLH VDD Vdc Min -- -- -- -- -- -- -- -- -- Typ (8.) 90 45 35 75 40 30 60 30 25 60 30 25 Max 180 90 70 150 80 60 125 75 55 125 75 55 Unit ns Output Rise Time tTLH = (1.2 ns/pF) CL + 30 ns tTLH = (0.5 ns/pF) CL + 20 ns tTLH = (0.4 ns/pF) CL + 15 ns Output Fall Time tTHL = (1.2 ns/pF) CL + 15 ns tTHL = (0.5 ns/pF) CL + 15 ns tTHL = (0.4 ns/pF) CL + 10 ns 5.0 10 15 tTHL ns 5.0 10 15 Turn-Off Delay Time tPLH = (1.5 ns/pF) CL + 35 ns tPLH = (0.2 ns/pF) CL + 20 ns tPLH = (0.15 ns/pF) CL + 17.5 ns Turn-On Delay Time tPHL = (1.0 ns/pF) CL + 10 ns tPHL = (0.3 ns/pF) CL + 15 ns tPHL = (0.2 ns/pF) CL + 15 ns tPLH ns 5.0 10 15 5.0 10 15 tPHL ns -- -- -- 7. The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter. 8. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD = -VGS 14 IOH 7 VSS VDS = VOH - VDD 7 VDD = VGS 14 IOL VSS VDS = VOL All unused inputs connected to ground. All unused inputs connected to ground. 0 -4.0 VGS = -5.0 Vdc -8.0 -12 -16 -20 -10 -10 Vdc a TA = -55C b TA = +25C c TA = +125C c b a c b c b a a -8.0 -6.0 -4.0 VDS, DRAIN VOLTAGE (Vdc) -2.0 -0 -15 Vdc 20 16 12 8.0 4.0 0 a c 0 2.0 a b c a b c a TA = -55C b TA = +25C c TA = +125C b 5.0 Vdc 10 Vdc VGS = 15 Vdc 4.0 6.0 VDS, DRAIN VOLTAGE (Vdc) 8.0 10
Figure 2. Typical Output Source Characteristics
Figure 3. Typical Output Sink Characteristics
These typical curves are not guarantees, but are design aids. Caution: The maximum current rating is 10 mA per pin.
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MC14007UB
VDD 500 F PULSE GENERATOR Vin 7 ID 14 VSS CL Vout Vout 0.01 F CERAMIC 20 ns Vin 90% 50% 10% tPHL 90% 50% 10% tTHL tTLH tPLH 20 ns VDD VSS VOH VOL
Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms
APPLICATIONS The MC14007UB dual pair plus inverter, which has access to all its elements offers a number of unique circuit applications. Figures 1, 5, and 6 are a few examples of the device flexibility.
+VDD 2 DISABLE 3 1 11 9 INPUT 10 12 OUTPUT C 9 8 DISABLE 6 7 Substrates of P-channel devices internally connected to VDD; Substrates of N-channel devices internally connected to VSS. INPUT 1 0 X X = Don't Care DISABLE 0 0 1 OUTPUT 0 1 OPEN A 6 5 3 4 7 B 10 VDD 14 OUT = A+B*C
13 11 12 8 2
1
OUTPUT
Figure 6. AOI Functions Using Tree Logic
Figure 5. 3-State Buffer
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MC14007UB
PACKAGE DIMENSIONS
P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE M
14 8
B
1 7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --10_ 0.38 1.01
A F N -T-
SEATING PLANE
L C
K H G D 14 PL 0.13 (0.005)
M
J M
DIM A B C D F G H J K L M N
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
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MC14007UB
PACKAGE DIMENSIONS
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --1.20 --0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 965-01 ISSUE O
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
b 0.13 (0.005)
M
A1 0.10 (0.004)
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CCC EE CCC EE
c
SECTION N-N -W-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --1.42 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.056
MC14007UB
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local Sales Representative.
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MC14007UB/D

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